Recently, a capacitive cell used in a VLSI (Very Large Scale Integration) such as a 64MDRAM using a tantalum oxide layer has been proposed to increase a capacitive value per a unit area.
In a conventional method for fabricating a capacitive cell, a tantalum oxide layer is formed on a lower electrode on a semiconductor substrate which is provided with a device separation region and a device formation region. Then, the tantalum oxide layer is processed to be fine in oxygen atmosphere by thermal treatment. After that, an upper electrode is formed on the tantalum oxide layer, so that a capacitive cell is fabricated.
According to the conventional method for fabricating a semiconductor device, however, there is a disadvantage in that a capacitive layer having a predetermined resistance for suppressing a leak current is not obtained, so that a reliability of a semiconductor device thus fabricated is low. That is, when a tantalum oxide layer having a thickness equal to a SiO.sub.2 film having a thickness of 30 .ANG. is formed as a capacitive layer, a voltage for a leak current of 10.sup.-8 A/cm.sup.2 is as low as 0.6 V. This voltage is defined "a leak-proof voltage" hereinafter. As a result, a semiconductor device having such a capacitive cell is difficult to be put to practical use.